The present invention relates generally to computing systems, and more specifically, to process identifier (PID) based transferring of cache information between caches in a multiprocessor computer processor.
A processor subsystem in a computing system may include multiple processor chips. There may be multiple processor cores on a single processor chip. Such multicore chips are used for many types of computing systems, including but not limited to desktops, servers, smartphones, and tablets. Caching is used in a processor subsystem to allow frequently-used data (for example, instruction data or operand data), to be easily accessed by a processor core without needing to search in a main memory of the computing system, thereby increasing the speed of processor operations. The cores in a processor subsystem may each have respective local caches, and cores on the same chip may additionally share a common higher-level cache. The local caches may be private, or may be shared with other processor cores in the subsystem in various topologies, for example, ring, bus or mesh.
When a core makes an access to its local cache, the core may find that the data it needs is not in the core's local cache (i.e., there is a local cache miss). The data may instead be located in another shared or local cache on the same chip or on another chip. The core that experienced the local cache miss may make a cache line transfer request to the cache subsystem to fetch the desired data to its local cache. Fetching of data from one cache to another may be a master/slave relationship. The core that needs the data is the master and makes the request to the cache subsystem, which is the slave. The cache subsystem may then locate the data in a particular local cache and returns it to the requestor. The most recent value of a particular storage location may be determined by the cache subsystem, and then be sent to the requester. The location process may involve determining whether the desired data already exists within the subsystem; if the data does not already exist within the cache subsystem the data may need to be retrieved from the main memory of the computing system. Intra-cache data transfers may be maintained on a per cache line basis and may be governed by cache protocols that are adapted by the particular processor to fit its architecture and design requirements.